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general description the ds2726 provides full charge and discharge protection for 5- to 10-cell lithium-ion (li+) battery packs. the protec- tion circuit monitors individual cell voltages to detect over- voltage and undervoltage conditions. protection against discharge overcurrent and short-circuit current is provided with user-selectable thresholds using external resistors. p-channel protection fets are employed high side and driven from on-chip 10v fet drivers. cell balancing can be enabled to ensure that all cells are equally charged. applications power tools electric bikes home appliances features ? complete protection for 5-cell to 10-cell li+ packs ? pin programmable for 5 to 10 cells ? internal cell-balancing circuit, shunts up to 300ma ? pin-programmable v ov threshold ? pin-programmable cell-balance voltage ? overdischarge current and short-circuit current set with external resistors ? overdischarge current and short-circuit current timeout delay set with external capacitors ? low power consumption: 60? (typ) ? low shutdown power consumption: 5? (typ) ? 7mm x 7mm, 32-pin tqfn lead-free package ds2726 5-cell to 10-cell li+ protector with cell balancing ________________________________________________________________ maxim integrated products 1 ordering information ds2726 v cc sel0 sel1 ovs0 ovs1 cbs0 cbs1 cbcfg sleep rsc rdoc sleep pkp- cscd v cc pkp+ v10 gnd pkp cdocd v in cc sns v09 v08 v07 v06 v05 v04 v03 v02 v01 v00 v in dc simplified typical application circuit 19-5482; rev 3; 8/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. * ep = exposed pad. pin configuration appears at end of data sheet. part temp range pin-package DS2726G+ -20c to +85c 32 tqfn-ep* DS2726G+t&r -20c to +85c 32 tqfn-ep*
ds2726 5-cell to 10-cell li+ protector with cell balancing 2 _______________________________________________________________________________________ absolute maximum ratings recommended dc operating conditions (t a = -20? to +85?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v00?10, pkp, rdoc, rsc pins relative to gnd .....................-0.3v to +60v voltage range on dc pin relative to v in ..............-12v to +0.3v voltage range on cc pin relative to pkp .............-12v to +0.3v voltage range on cscd, sel0, sel1, ovs0, ovs1, cbs0, cbs1, sleep, cbcfg, v cc pins relative to gnd ...................-0.3v to +6.0v human body model (hbm) esd limit of v05?09, pkp, cc, dc..................................................?00v all other pins ...................................................................?kv voltage range on any v x to v x-1 (v10 to v09).......-0.3v to +12v continuous power dissipation (t a = +70?) tqfn (derate 37mw/? above +70?) .....................2963mw junction temperature ......................................................+150? operating temperature range ...........................-20? to +85? storage temperature range .............................-55? to +125? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units supply range v in (notes 1, 2, 3, 4) 5 50 v input range: sel0, sel1, ovs0, ovs1, cbs0, cbs1, cscd, cdocd, sleep, cbcfg (note 1) -0.3 v cc + 0.3 v dc electrical characteristics (t a = -20? to +85?.) parameter symbol conditions min typ max units i dd protector mode, no fault (notes 4, 9) 70 90 i dd_bal load balancing (note 11) 400 supply current i sleep sleep mode 5.0 7.5 a v00Cv10 leakage current all cell voltages = 4.2v (note 10) -2 +2 a input logic-high: sel0, sel1, ovs0, ovs1, cbs0, cbs1, sleep v ih i load = 2a (notes 1, 5) v cc - 0.4 v input logic-mid: sel0, sel1, ovs0, ovs1, cbs0, cbs1, sleep v im i load = 0 (notes 1, 5) 1.30 1.65 2.00 v input logic-low: sel0, sel1, ovs0, ovs1, cbs0, cbs1, sleep v il i load = -2a (notes 1, 5) v gnd + 0.4 v v cc output voltage i load = 1ma (notes 1, 5, 8) 4.75 5.00 5.25 v v cc dropout voltage (note 6) 5.5 v output low: cc v olcc i ol = -100a, v pkp 13v (notes 3, 5) v pkp - 12 v pkp - 8 v cc = v olcc + 2v -3 -1 output low: cc driver current cc = v ohcc - 1v -15 -7 ma
ds2726 5-cell to 10-cell li+ protector with cell balancing _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (t a = -20? to +85?.) parameter symbol conditions min typ max units output high: cc v ohcc i oh = 100a v pkp - 0.5 v pkp + 0.3 v cc = v olcc + 2v 7 15 output high: cc driver current cc = v ohcc - 1v 0.5 1.5 ma output low: dc v oldc i ol = -100a, v in 13v (notes 3, 5) v in - 12 v in - 8 v dc = v oldc + 2v -3 -1 output low: dc driver current dc = v ohdc - 1v -15 -7 ma output high: dc v ohdc i oh = 100a v in - 0.5 v in + 0.3 v dc = v oldc + 2v 7 15 output high: dc driver current dc = v ohdc - 1v 0.5 1.5 ma maximum balancing current i bal 300 ma balance fet: on-resistance i bal = 180ma 1.7 3.2 7.0 electrical characteristics: protection circuit (t a = 0? to +50?.) parameter symbol conditions min typ max units ovs1 = gnd, ovs0 = gnd 4.05 4.10 4.15 ovs1 = gnd, ovs0 = n.c. 4.10 4.15 4.20 ovs1 = gnd, ovs0 = v cc 4.15 4.20 4.25 ovs1 = n.c., ovs0 = gnd 4.20 4.25 4.30 ovs1 = n.c., ovs0 = n.c. 4.25 4.30 4.35 ovs1 = n.c., ovs0 = v cc 4.30 4.35 4.40 ovs1 = v cc , ovs0 = gnd 4.35 4.40 4.45 ovs1 = v cc , ovs0 = n.c. 4.40 4.45 4.50 overvoltage detect v ov ovs1 = v cc , ovs0 = v cc 4.45 4.50 4.55 v charge-enable voltage v ce v ovmin - 0.15 v ovmax - 0.15 v charge-balance voltage v bal v bal lowest typical set point limited to 3.75v v ovmin - cell- balancing threshold v ovmax - cell- balancing threshold v undervoltage release v uvrel 2.7 2.8 2.9 v undervoltage detect v uv 2.2 2.3 2.4 v rdoc, rsc output current v in - v rdoc = v in - v rsc = 2v 0.95 1.00 1.05 a rdoc, rsc input offset voltage -3 +3 mv
ds2726 5-cell to 10-cell li+ protector with cell balancing 4 _______________________________________________________________________________________ note 1: all voltages relative to gnd. note 2: voltages below this level cannot be monitored; therefore, cc and dc are off below this value. note 3: full-gate drive is not achieved until the voltage source for the gate driver (v pkp or v vin ) is above 13v. note 4: with 10? decoupling capacitor. note 5: i load is the current load on the pin specified in the parameter. note 6: v cc cannot meet specification if v vin is below this value. note 7: capacitance tolerance introduces additional error. note 8: with 0.1? decoupling capacitor. note 9: current is an average. spikes up to 200? when measuring cell voltages. note 10: current is an average. spikes up to 15? when measuring cell voltages. note 11: current depends on the number of cells being balanced. note 12: includes switching time and comparator delay with 25mv overdrive. electrical characteristics: protection circuit (continued) (t a = 0? to +50?.) parameter symbol conditions min typ max units overvoltage delay t ovd 128 x t docdmin 128 x t docdmax ms undervoltage delay t uvd 128 x t docdmin 128 x t docdmax ms c docd = 100pf (notes 7, 12) 2.56 3.20 3.84 discharge overcurrent delay t docd c docd = 1000pf (notes 7, 12) 25.6 32.0 38.4 ms c scd = 100pf (notes 7, 12) 45 58 72 short-circuit delay t scd c scd = 1000pf (notes 7, 12) 405 508 612 s charger-detect threshold (v pkp - v vin ) v cdet 3 17 mv test threshold v tp doc conditions 0.8 1.2 1.7 v doc condition, v in - v pkp = 2v 68 120 200 a test current i tst doc condition, v in - v pkp = 50v 0.5 1.20 1.8 ma
ds2726 5-cell to 10-cell li+ protector with cell balancing _______________________________________________________________________________________ 5 typical operating characteristics (t a = +25?, unless otherwise noted.) ov accuracy vs. temperature ds2726 toc01 temperature ( c) ov accuracy (v) 60 35 10 -15 -0.007 -0.005 -0.003 -0.001 0.001 0.003 0.005 0.007 0.009 -0.009 -40 85 uv accuracy vs. temperature ds2726 toc02 temperature ( c) uv accuracy (v) 60 35 -15 10 0.002 0.004 0.006 0.008 0.012 0.010 0.014 0 -40 85 test current vs. (v vin - v pkp ) ds2726 toc03 (v vin - v pkp ) (v) i tst (ma) 50 40 30 20 10 0.2 0.4 0.6 0.8 1.0 1.2 0 060 v tp = 1.16v discharge overcurrent delay (cdocd = 1000pf, r doc = 110k with r ds_on = 2.75k ) time (ms) vgs discharge fet (v) load current (a) 40 30 20 10 -9 -7 -5 -3 -1 1 -11 0 10 20 30 40 50 -10 050 ds2726 toc04 doc condition vgs discharge fet discharge overcurrent threshold load current short-circuit delay (cdocd = 1000pf, rsc = 247.5k with r ds_on = 2.75m ) time ( s) 100 50 -9 -7 -5 -3 -1 1 -11 0 vgs discharge fet (v) load current (a) 20 40 60 80 100 120 0 ds2726 toc05 load current short-circuit condition short-circuit threshold vgs discharge fet fet turn-off time (with 460nc total gate charge) ds2726 toc06 20 s/div 5v/div 180 160 20 40 60 120 100 80 140 5 10 15 20 25 30 35 40 200
ds2726 5-cell to 10-cell li+ protector with cell balancing 6 _______________________________________________________________________________________ v ov , v bal , v ce , v uv v10 v in v in dc ds2726 sns 10v 10v v09 v ov , v bal , v ce , v uv v08 v ov , v bal , v ce , v uv v07 v ov , v bal , v ce , v uv v06 v ov , v bal , v ce , v uv v05 v ov , v bal , v ce , v uv v04 v ov , v bal , v ce , v uv v03 rsc cscd sns rdoc cdocd v ov , v bal , v ce , v uv v02 v ov , v bal , v ce , v uv v01 v ov , v bal , v ce , v uv v00 cc v cc v cc pkp pkp+ r tst logic v in sel0 sel1 ovs0 ovs1 cbs0 cbs1 cbcfg sleep pkp- gnd v reg t scd t docd v cdet figure 1. block diagram
ds2726 5-cell to 10-cell li+ protector with cell balancing _______________________________________________________________________________________ 7 pin description pin name function 1 rsc short-circuit voltage threshold. the resistor from this pin to the positive terminal of the cell stack selects the threshold voltage for a short-circuit condition in the discharge direction. 2 rdoc discharge overcurrent voltage threshold. the resistor from this pin to the positive terminal of the cell stack selects the threshold voltage for an overcurrent condition in the discharge direction. 3 v cc regulator supply output. v cc supplies power to internal circuits and can be used to pull configuration pins to v ih . it should be bypassed to gnd with at least a 0.1f ceramic capacitor. 4, 5 sel0, sel1 select number of cells in the battery stack. this input is a three-level input. connect to ground or v cc for a logic-low or logic-high, respectively. leave unconnected to achieve the midthreshold. see table 2 for how to drive this pin for a particular number of cells. 6 cdocd discharge overcurrent delay time. connect a capacitor from this pin to gnd to select the amount of time for which a discharge overcurrent condition must persist before shutting off the dc fet. 7 sleep sleep-mode select input. driving this pin to a logic-low level forces the part into the lowest power state. the part exits sleep mode once a charge voltage is applied. when cbcfg is high, a logic-high on this pin enables cell balancing. 8 cscd short-circuit current delay time. connect a capacitor from this pin to gnd to select the amount of time for which a short-circuit current condition must persist before shutting off the dc fet. 9 cbcfg charge-balance configuration input. when this pin is at a logic-low, charge balancing is enabled if v pkp > v vin + v cdet . when this pin is at a logic-high, charge bal ancing is enabled if the sleep pin is at a logic-high. 10, 11 cbs0, cbs1 select cell-balancing voltage. this input is a three-level input. connect to gr ound or v cc for a logic-low or logic-high, respectively. leave unconnected to achieve the midthreshold. see table 4 for how to drive this pin for a particular cell-balancing voltage threshold. 12, 13 ovs0, ovs1 select overvoltage threshold. this input is a three-level input. connect to ground or v cc for a logic-low or logic-high, respectively. leave unconnected to achieve the midthreshold. see table 3 for how to drive this pin for a particular overvoltage threshold. 14, 30 n.c. no connection. not internally connected. 15 gnd ground. connect to the negative terminal of the lowest voltage cell. 16 v00 negative terminal voltage sense. connect to the negative terminal of the 1st cell in the battery stack. 17 v01 cell 01 voltage sense. connect to the positive terminal of the 1st cell in the battery stack. 18 v02 cell 02 voltage sense. connect to the positive terminal of the 2nd cell in the battery stack. 19 v03 cell 03 voltage sense. connect to the positive terminal of the 3rd cell inf the battery stack. 20 v04 cell 04 voltage sense. connect to the positive terminal of the 4th cell in the battery stack. 21 v05 cell 05 voltage sense. connect to the positive terminal of the 5th cell in the battery stack. 22 v06 cell 06 voltage sense. connect to the positive terminal of the 6th cell in the battery stack. 23 v07 cell 07 voltage sense. connect to the positive terminal of the 7th cell in the battery stack. 24 v08 cell 08 voltage sense. connect to the positive terminal of the 8th cell in the battery stack. 25 v09 cell 09 voltage sense. connect to the positive terminal of the 9th cell in the battery stack. 26 v10 cell 10 voltage sense. connect to the positive terminal of the 10th cell in the battery stack. 27 v in connect to the most positive cell terminal 28 dc discharge control output. dc controls the gate of the discharge fet. driven from v in to v oldc to turn on and turn off the discharge fet.
ds2726 5-cell to 10-cell li+ protector with cell balancing 8 _______________________________________________________________________________________ pin description (continued) pin name function 29 sns sense input. connect to the drains of the charge and discharge fets. used as a voltage reference for detecting short-circuit and discharge overcurrent conditions. 31 cc charge control output. cc controls the gate of the charge fet. driven from pkp to v olcc to turn on and turn off the charge fet. 32 pkp pack positive. the voltage on pkp is used to detect charger-attach and protection-release conditions. ep exposed pad. connect to the negative terminal of the lowest voltage potential cell. rsc rdoc sel0 v cc v08 v07 v06 v05 v04 v03 v02 v01 cbcfg v00 gnd n.c. ovs1 ovs0 cbs1 cbs0 pkp cc n.c. sns dc v in v10 v09 150 150 150 15 v in 205k sel1 cdocd cscd sleep 82.5k 150 60v 1a 1 f 0.1 f 1 f 1 f 10 f 1 f v10 1k 1k 1k 1k 1k 1k v cc 150 0.1 f 10k 1k 6.2v 150k sleep pkp- pkp+ ds2726 v09 v08 v07 v06 v05 v04 v03 v02 v01 v00 figure 2. typical application circuit
detailed description the ds2726 provides the protection features for a 5-cell to 10-cell li+ battery pack. the li+ protection cir- cuit allows for pin-configured selection of ov threshold and the cell-balancing threshold. doc and sc thresh- olds and delays are component programmable. sleep mode sleep mode is a low-power state where the fets are open and the ic is not monitoring voltages. during wake mode, the ic measures voltages and drives the fets to the appropriate state. upon initial connection to cells, the ds2726 enters sleep mode. the ic also enters sleep mode if a uv condition is detected. sleep mode can be initiated any time by pulling the sleep pin low while a charger- detect condition does not exist. during sleep mode there is a pulldown current from pkp to gnd. v pkp must be within v tp of v vin (v pkp > v vin - v tp ) to exit wake from sleep mode. when a charger is detected and v cc achieves regula- tion, the part measures all cells for undervoltage and overvoltage. then the ic begins controlling the cc and dc fets as shown in table 1. care should be taken to ensure that the sleep pin is not held low during a wake condition. charger detect the ds2726 has two different methods for detecting a charger connection. the methods are pin programma- ble at the cbcfg pin. if cbcfg is pulled to gnd, then charge detection occurs when v pkp > v vin + v cdet . if cbcfg is pulled to v cc , then charge detection occurs when the sleep pin is driven to a logic-high state. li+ protection circuitry in active mode, the ds2726 constantly monitors v00 v10 to protect the battery from overvoltage and under- voltage. the voltage on the sns pin is monitored and compared to the voltages on rdoc and rsc to protect against excessive discharge currents (discharge over- current and short circuit). table 1 summarizes the con- ditions that activate the protection circuit, the response of the ds2726, and the thresholds that release it from a protection state. ds2726 5-cell to 10-cell li+ protector with cell balancing _______________________________________________________________________________________ 9 activation condition* threshold delay response release threshold overvoltage (ov) v cell > v ov t ovd cc off v cell < v ce cbcfg < v il and v cell < v uv_rel , then v pkp > v vin + v cdet (note 13) cbcfg < v il and v cell > v uv_rel , then v pkp > v vin - v tp undervoltage (uv) (note 15) v cell < v uv t uvd cc off, dc off, sleep mode cbcfg > v ih then sleep > v ih and v pkp > v vin - v tp discharge overcurrent (doc) (note 15) v sns < v rdoc t docd dc off v pkp > v vin - v tp (note 14) short circuit (sc) v sns < v rsc t scd dc off v pkp > v vin - v tp (note 15) table 1. li+ protection conditions and ds2726 responses *all voltages are with respect to gnd. cc off: v cc = v pkp , dc off: v dc = v vin . note 13: the dc fet remains off until v cell > v uv_rel . note 14: with test current i tst flowing from v in to pkp. note 15: if a doc condition persists indefinitely and a uv condition is reached, the ic does not enter sleep mode.
ds2726 li+ protection conditions overvoltage, ov. if any cell voltage (v cell ) exceeds the overvoltage threshold, v ov , for a period longer than overvoltage delay, t ovd , the ds2726 shuts off the external charge fet. when v cell falls below the charge-enable threshold v ce , the ds2726 turns the charge fet on. the discharge fet remains enabled during the overvoltage event. care should be taken while discharging during an ov condition because the current drawn by the load is going through the body diode of the cc fet. undervoltage, uv. if v cell drops below the undervolt- age threshold, v uv , for a period longer than undervolt- age delay, t uvd , the ds2726 shuts off the charge and discharge fets and enters sleep mode. the device remains in sleep mode until a charger is detected, at which point the ds2726 wakes up and enables the cc fet. the dc fet remains disabled until every cell is above the v uv_rel threshold. care should be taken while charging during a uv event because the charge current is flowing through the body diode of the dc fet. discharge overcurrent, doc. if v sns is less than v rdoc for a period longer than t docd , the ds2726 shuts off the external discharge fet. the discharge current path is not reestablished until v pkp rises above v vin - v tp . the ds2726 provides a test current of value i tst from the pkp pin to the v in pin to detect the removal of the offending low-impedance load. i tst is not disabled if an undervoltage condition is reached. short circuit, sc. if v sns is less than v rsc for a peri- od longer than short-circuit delay t scd , the ds2726 shuts off the external discharge fet. the discharge current path is not reestablished until v pkp rises above v vin - v tp . the ds2726 provides a test current of value i tst from the pkp pin to the v in pin to detect the removal of the short. i tst is disabled if an undervoltage condition is reached. summary. all the protection conditions described are logic ored to affect the cc and dc outputs: dc = (undervoltage) or (discharge overcurrent) or (short circuit) cc = (overvoltage) or (undervoltage and charger detect ) 5-cell to 10-cell li+ protector with cell balancing 10 ______________________________________________________________________________________ v ov v ce v uv v cell v sns v rsc v rdoc v in t ovd t ovd t uvd t uvd t ocd t scd charge discharge power mode active sleep cc dc v ohcc v olcc v oldc v ohdc v uv_rel figure 3. li+ protection circuitry example waveforms
configuration for number of cells the ds2726 protects 5 to 10 li+-based cells connect- ed in series. the number of cells is configured using the sel0 and sel1 pins according to table 2. pin v10 should always be connected to the positive ter- minal of the battery stack regardless of the number of cells in the stack. cell connections that are not in use for battery stacks with fewer than 10 cells should be shorted to the cell connection below it. for example, a stack with 9 cells would have v9 shorted to v8 and v8 connected to the positive terminal of the 8th cell; a stack with 8 cells would have v9 shorted to v8 shorted to v7 and v7 connected to the positive terminal of the 7th cell, and so on (see figure 4). cell connection order care must be taken when connecting cells to the ds2726 to avoid damaging the device. gnd should be connected first, then v in . next, v0 should be connect- ed, then v1 and so on until v10 is connected last. ds2726 5-cell to 10-cell li+ protector with cell balancing ______________________________________________________________________________________ 11 9 cells v10 v09 v08 v07 v06 v05 v04 v03 v02 v01 v00 8 cells v10 v09 v08 v07 v06 v05 v04 v03 v02 v01 v00 7 cells v10 v09 v08 v07 v06 v05 v04 v03 v02 v01 v00 6 cells v10 v09 v08 v07 v06 v05 v04 v03 v02 v01 v00 5 cells v10 v09 v08 v07 v06 v05 v04 v03 v02 v01 v00 figure 4. cell bypassing connection table 2. number of cells configuration number of series-connected cells pin 5 6 7 8 9 10101010 sel0 v il v im v ih v il v im v ih v il v im v ih sel1 v il v il v il v im v im v im v ih v ih v ih note: the dc fet remains off until v cell > v uv_rel .
ds2726 configuration of overvoltage threshold the ds2726 allows the ov threshold to be set using the overvoltage select pins. the ov threshold is configured using the ovs0 and ovs1 pins according to table 3. enabling cell balancing for cell balancing to begin the ds2726 must detect a charger. the charge-balancing configuration pin (cbcfg) controls how the ic detects a charger. if cbcfg is pulled to gnd, balancing is enabled when the charge-current comparator detects a charger. this detection occurs when v pkp > v vin + v cdet . if cbcfg is pulled to v cc , cell balancing is enabled when the sleep pin is driven to a logic-high state. note that cell balancing must be enabled and a valid cell-balancing voltage must exist for cell balancing to occur. configuration of cell-balancing voltage threshold the ds2726 allows the cell-balancing threshold to be set using the cell-balance select pins. the threshold is config- ured using the cbs0 and cbs1 pins according to table 4. setting the cell-balancing voltage threshold to zero dis- ables the cell-balancing circuitry. the nominal cell-bal- ancing voltage is never allowed a value below 3.75v. setting the ovs0 and ovs1 pins low while the cbs0 and cbs1 pins are high results in a cell-balancing volt- age (v bal ) of 3.75v. nominal cell-balancing voltage: v bal = v ov ?cell-balancing voltage threshold balancing begins when any cell? voltage is greater than v bal . when the balancing condition is met and cell balancing is enabled, the corresponding internal fet (from v x to v x-1 ) is enabled, shunting a portion of the charge current around the cell. the external resis- tors on v00?10 should be chosen to limit the balanc- ing current to a maximum of 200ma. this prevents damaging the internal cell-balancing fets. the ds2726 has three distinct states during balancing. a voltage measurement state of 5/32 t ocd time periods is followed by a balancing state where even numbered cells are balanced for 123/32 t ocd time periods. another voltage measurement state of 5/32 t ocd time periods then occurs. this is followed by a balancing state where odd numbered cells are balanced for 123/32 t ocd time periods. this gives an average bal- ancing current of approximately half the maximum bal- ance current. cell balancing terminates when all cell voltages are greater than v bal . see the measurement sequence section. 5-cell to 10-cell li+ protector with cell balancing 12 ______________________________________________________________________________________ table 3. ov threshold configuration nominal ov threshold (v) pin 4.10 4.15 4.20 4.25 4.30 4.35 4.40 4.45 4.50 ovs0 v il v im v ih v il v im v ih v il v im v ih ovs1 v il v il v il v im v im v im v ih v ih v ih table 4. cell-balancing threshold configuration cell-balancing voltage threshold (offset from v ov ) (v) pin 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 cbs0 v il v im v ih v il v im v ih v il v im v ih cbs1 v il v il v il v im v im v im v ih v ih v ih
ds2726 5-cell to 10-cell li+ protector with cell balancing ______________________________________________________________________________________ 13 setting the short-circuit threshold and delay time the ds2726 allows the selection of a short-circuit cur- rent threshold. this threshold is set using a resistor from the rsc pin to the positive terminal of the cell stack. the rsc pin sinks 1? (nominal). the short-cir- cuit comparator triggers when the voltage on the sns pin is less than the voltage on the rsc pin. for exam- ple, assume a 500k resistor is used on rsc, along with a dc fet with an r ds_on of 10m . this corre- sponds to an rsc voltage of 500k x 1? = 0.5v. because the fet is 10m , the short-circuit threshold is 0.5v/10m = 50a: the ds2726 allows for a delayed reaction to a short-cir- cuit event. the short threshold must persist for the entire delay time before the dc fet begins to turn off (actual turn-off time varies based on the gate capaci- tance of the dc fet; see the dc pin drive capabilities in the dc electrical characteristics table for more details). the short-circuit delay time is set using a capacitor on the cscd pin. the short-circuit delay time can be calculated by the equation: t scd = c scd x 500k be sure to select threshold and delay times that fall within the safe operating area of the fets chosen for dc and cc. setting the discharge overcurrent threshold and delay time the ds2726 allows the selection of a discharge over- current threshold. this threshold is set using a resistor from the rdoc pin to the positive terminal of the cell stack. the rdoc pin sinks 1? (nominal). the overcur- rent circuit comparator triggers when the voltage on the sns pin is less than the voltage on the rdoc pin. for example, assume a 200k resistor is used on rdoc, along with a dc fet with an r ds_on of 10m . this corresponds to a voltage on rdoc of 200k x 1? = 0.2v. because the fet is 10m , the discharge overcur- rent threshold is 0.2v/10m = 20a: the ds2726 allows for a delayed reaction to a dis- charge overcurrent event. the discharge overcurrent threshold must persist for the entire delay time before the dc fet begins to turn off (actual turn-off time varies based on the gate capacitance of the dc fet; see dc pin drive capabilities in the dc electrical characteristics table for more details). the discharge overcurrent delay time is set using a capacitor on the cdocd pin. the discharge overcurrent delay can be calculated by the equation: t docd = c docd x 32m be sure to select threshold and delay times that fall within the safe operating area for the fets chosen for dc and cc. if the voltage on the cdocd pin is within approximately 1v of v cc or gnd, the condition is considered to be a fault, and the cc and dc outputs are disabled. this results in a delay before enabling the fets when the part awakens from sleep mode. this delay occurs until the voltage on cdocd reaches an acceptable level. this is a function of the capacitor on cdocd. the cdocd startup delay is in addition to a typical regulator startup of 100?, and is given by the equation: startup delay 100? + c docd x 1.65m be sure to select threshold and delay times that fall within the safe operating area for the fets chosen for dc and cc. i ? r r doc doc ds on = 1 _ i ? rsc r sc ds on = 1 _
ds2726 measurement sequence the period with which the ds2726 measures voltages is a function of the discharge overcurrent delay time, t docd . figure 5 illustrates the measurement sequence. one measurement period: 4 x t docd v uv , v uv_rel , v ce , v ov , and v bal are measured for all cells: 5 x t docd /32 chip performs balancing on even cells: 123 x t docd /32 one measurement period: 4 x t docd v uv , v uv_rel , v ce , v ov , and v bal are measured for all cells: 5 x t docd /32 chip performs balancing on odd cells: 123 x t docd /32 one cell-balancing period: 8 x t docd overvoltage and undervoltage delay time cell voltages are measured simultaneously and then sequentially compared to each of the five thresholds v uv , v uv_rel , v ce , v ov , and v bal . this sequence is repeated every four t docd intervals. overvoltage and undervoltage conditions are time qualified and there- fore not recognized immediately. if an overvoltage con- dition exists on any cell for 32 intervals consecutively (t ovd = 4 x 32 x t docd = 128 x t docd ), an overvoltage condition is recognized, and the cc fet is turned off. if an undervoltage condition exists on any cell for 32 intervals consecutively (t uvd = 4 x 32 x t docd = 128 x t docd ) an undervoltage condition is recognized, the cc and dc fets are turned off, and sleep mode is entered. 5-cell to 10-cell li+ protector with cell balancing 14 ______________________________________________________________________________________ v uv , v uv_rel , v ce , v ov , and v bal are measured for all cells v uv , v uv_rel , v ce , v ov , and v bal are measured for all cells cell balancing is performed on even- numbered cells cell balancing is performed on odd- numbered cells ... ... ... 12345123 12312345123 123 123456 32 one measurement period one cell-balancing period 128 t docd , part responds to v uv , v uv_rel , v ce , v ov , and v bal condition t docd / 32 4 t docd 4 t docd 4 t docd 4 t docd 4 t docd 4 t docd 4 t docd t docd / 32 t docd / 32 t docd / 32 t docd / 32 t docd / 32 t docd / 32 t docd / 32 t docd / 32 t docd / 32 t docd / 32 t docd / 32 t docd / 32 t docd / 32 t docd / 32 t docd / 32 t docd / 32 t docd / 32 figure 5. cell balancing and measurement periods
ds2726 5-cell to 10-cell li+ protector with cell balancing ______________________________________________________________________________________ 15 ds2726 tqfn (7mm top view 29 30 28 27 12 11 13 rdoc sel0 sel1 cdocd sleep 14 rsc v07 v05 v04 v08 v03 v02 12 dc 4567 23 24 22 20 19 18 sns n.c. n.c. ovs1 ovs0 cbs1 v cc v06 3 21 31 10 cc cbs0 ep 32 9 pkp cbcfg v in 26 15 gnd v10 25 16 v00 cscd v01 8 17 v09 + pin configuration package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 32 tqfn-ep t3277+2 21-0144 90-0125
ds2726 5-cell to 10-cell li+ protector with cell balancing maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 4/08 initial release. 1 9/08 deleted the 50mv overvoltage accuracy from the features section, added the cell connection order section, corrected wording mistake in the configuration of cell- balancing voltage threshold section involving minimum cell-balancing voltage configuration. 1, 11, 12 2 1/09 corrected pfet drawings in schematics, added the pkp, cc, dc pins to the human body model (hbm) esd limit in the absolute maximum ratings . 1, 2, 6, 8 3 8/10 changed the operating temperature range from -40c to +85c to -20c to +85c in the absolute maximum ratings . 2

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